XPGA Datasheet, PDF (13/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 13. EBR Synchronous Read Timing Diagram
ispXPGA Family Data Sheet
CLK
CE
WE
OE
DATA
ADDR
t_EBCES
t_EBWES
t_EBCPW
Invalid Data
t_EBWEDIS
t_EBADDS
t_EBCO
t_EBOEDIS
Valid Data
t_EBADDH
t_EBCEH
t_EBWEH
t_EBOEEN
t_EBWEEN
Valid Data
Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high and the
write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock
edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the
synchronous write timing.
Figure 14. EBR Synchronous Write Timing Diagram
CLK
t_EBPW
WE
t_EBWES
t_EBWEH
DATA
t_EBDATAH
t_EBDATAS
ADDR
t_EBADDH
t_EBADDS
WRITE
WRITE
Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the
read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15
illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note num-
ber TN1028 ispXPGA Memory Usage Guidelines, available at www.latticesemi.com.
Figure 15. EBR Asynchronous Read Timing Diagram
WE
OE
DATA
ADDR
t_EBWEDIS
Invalid Data
DATA0
ADDR0
t_{EBARAD_H}
t_EBARADO
t_EBOEDIS
DATA1
ADDR1
t_EBOEEN
t_EBWEEN
DATA1
ADDR2
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