XPGA Datasheet, PDF (29/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA EBR Timing Parameters
Parameter
Description
Synchronous Write
t_{EBSWAD_S}
Address Setup Delay
t_{EBSWAD_H}
Address Hold Delay
t_EBSWCPW
Clock Pulse Width
t_{EBSWWE_S}
Write Enable Setup Time
t_{EBSWWE_H}
Write Enable Hold Time
t_{EBSWD_S}
Data Setup Time
t_{EBSWD_H}
Data Hold Time
Synchronous Read
t_{EBSR_CO}
Clock to Data Delay
t_{EBSRAD_S}
Address Setup Delay
t_{EBSRAD_H}
Address Hold Delay
t_EBSRCPW
Clock Pulse Width
t_{EBSRCE_S}
Clock Enable Setup Time
t_{EBSRCE_H}
Clock Enable Hold Time
t_{EBSRWE_S}
Write Enable Setup Time
t_{EBSRWE_H}
Write Enable Hold Time
t_EBSRWEEN
Write Enable to Data Enable Time
t_EBSRWEDIS
Write Enable to Data Disable Time
t_EBSREN
Output Enable to Data Enable Time
t_EBSRDIS
Output Enable to Data Disable Time
Asynchronous Read
t_EBARADO
t_{EBARAD_H}
t_EBARWEEN
t_EBARWEDIS
t_EBAREN
t_EBARDIS
Address to New Valid Data Delay
Address to Previous Valid Data Delay
Write Enable to Data Enable Time
Write Enable to Data Disable Time
Output Enable to Data Enable Time
Output Enable to Data Disable Time
ispXPGA Family Data Sheet
-4
Min.
Max.
0.61
—
-0.39
—
—
3.40
-0.12
—
0.16
—
0.28
—
-0.26
—
—
2.19
0.10
—
-0.07
—
—
3.40
-1.71
—
1.69
—
-0.17
—
0.12
—
—
1.05
—
1.02
—
1.05
—
0.86
—
2.46
—
2.17
—
1.04
—
1.01
—
1.05
—
0.86
-3
Min.
Max.
Units
0.70
—
ns
-0.33
—
ns
—
3.91
ns
-0.10
—
ns
0.18
—
ns
0.32
—
ns
-0.22
—
ns
—
2.52
ns
0.12
—
ns
-0.06
—
ns
—
3.91
ns
-1.45
—
ns
1.94
—
ns
-0.14
—
ns
0.14
—
ns
—
1.21
ns
—
1.17
ns
—
1.21
ns
—
0.99
ns
—
2.83
ns
—
2.50
ns
—
1.20
ns
—
1.16
ns
—
1.21
ns
—
0.99
ns
Timing v.2.0
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