I960 Datasheet, PDF (8/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
2.0 FUNCTIONAL OVERVIEW
As indicated in Figure 1, the 80960Rx combines
many features with the 80960JF to create an intelli-
gent I/O processor. Subsections following the figure
briefly describe the main features; for detailed func-
tional descriptions, refer to the i960^® RP Micropro-
cessor User’s Guide (272736).
The PCI bus is an industry standard, high perfor-
mance, low latency system bus that operates up to
132 Mbyte/s. The 80960Rx, a multi-function PCI
device, is fully compliant with the PCI Local Bus
Specification Revision 2.1. Function 0 is the PCI-to-
PCI bridge unit; Function 1 is the address translation
unit.
The PCI-to-PCI bridge unit is the connection path
between two independent 32-bit PCI buses and
provides the ability to overcome PCI electrical load
limits. The addition of the i960 core processor brings
intelligence to the bridge.
The 80960Rx, object code compatible with the i960
core processor, is capable of sustained execution at
the rate of one instruction per clock.
The local bus, a 32-bit multiplexed burst bus, is a
high-speed interface to system memory and I/O. A
full complement of control signals simplifies the
connection of the 80960Rx to external components.
Physical and logical memory attributes are
programmed via memory-mapped control registers
(MMRs), an extension not found on the i960 Kx, Sx
or Cx processors. Physical and logical configuration
registers enable the processor to operate with all
combinations of bus width and data object align-
ment.
Local Memory
I²C Serial Bus
I/O APIC Bus
Memory
Controller
i960^® JF
Core
Processor
I²C Bus
Interface Unit
I/O APIC Bus
Interface Unit
Internal
Arbitration
Two DMA
Channels
Primary ATU
Address
Translation
Unit
Primary PCI Bus
Local Bus
Message
Unit
PCI-to-PCI
Bridge Unit
One DMA
Channel
Secondary ATU
Address
Translation
Unit
Secondary PCI Bus
Secondary
PCI Arbitration
Unit
Figure 1. i960^® Rx I/O Processor at 3.3 V Functional Block Diagram
2
ADVANCE INFORMATION