I960 Datasheet, PDF (44/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 22. Synchronous Input Timings
Sym
Parameter
Min Max Units Notes
T_IS1 Input Setup to S_CLK — NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#, 6
DP3:0#
ns (1,2)
T_IS1A Input Setup to S_CLK — for all accesses except Expansion ROM 6
Accesses — AD31:0 only
ns (1,2)
T_IS1B Input Setup to S_CLK during Expansion ROM Accesses —
8
AD31:0 only
ns (1,2)
T_IH1 Input Hold from S_CLK — AD31:0, NMI#, XINT7:4#,
S_INT[A:D]#/XINT3:0#, DP3:0#
2
ns (1,2,4)
T_IS2 Input Setup to S_CLK — RDYRCV# and HOLD
T_IH2 Input Hold from S_CLK — RDYRCV# and HOLD
T_IS3 Input Setup to S_CLK — LOCK#/ONCE#, STEST
T_IH3 Input Hold from S_CLK — LOCK#/ONCE#, STEST
T_IS4 Input Setup to S_CLK — DREQ#
T_IH4 Input Hold from S_CLK — DREQ#
T_IS5 Input Setup to S_CLK — PCI Signals Except P_GNT#,
S_REQ0#/S_GNT#, and S_REQ5:1#
10
ns (2)
2
ns (2)
7
ns (1,2)
3
ns (1,2)
12
ns (2)
7
ns (2)
7
ns (2)
T_IH5 Input Hold from S_CLK — PCI Signals
0
T_IS6 Input Setup to S_CLK — P_RST#
6
T_IH6 Input Hold to S_CLK — P_RST#
2
T_IS7 Input Setup to S_CLK — P_GNT#
10
T_IS8 Input Setup to S_CLK — S_REQ0#/S_GNT# and S_REQ5:1#
12
T_IS9 Input Setup to P_RST# —
7
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
ns (2,4)
ns (2,3)
ns (2,3)
ns (2)
ns (2)
ns (1,2,4)
T_IH9 Input Hold from P_RST# —
3
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
ns (1,2,4)
NOTES:
1. Setup and hold times must be met for proper processor operation. NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# may be
synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
For asynchronous operation, NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# must be asserted for a minimum of two S_CLK
periods to guarantee recognition.
2. See Figure 12, TIS and TIH Input Setup and Hold Waveform (pg. 46).
3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
4. Guaranteed by design. May not be 100% tested.
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