I960 Datasheet, PDF (49/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 30. APIC Bus Interface Signal Timings (Sheet 2 of 2)
Symbol
Parameter
Min
T_APIS1
Input Setup to PICCLK — PICD1:0
3
T_APIH1
Input Hold from PICCLK — PICD1:0
2.5
T_APOF
Output Float Delay from PICCLK — PICD1:0
4
T_APOVI
Output Valid Delay from PICCLK — PICD1:0 (High to Low) 4
NOTES:
1. Not tested.
Max
16
22
Units
ns
ns
ns
ns
Notes
(1)
4.4.5 I²C Interface Signal Timings
Table 31. I²C Interface Signal Timings
Symbol
Parameter
F_SCL
T_BUF
SCL Clock Frequency
Bus Free Time Between STOP and START
Condition
T_HDSTA Hold Time (repeated) START Condition
T_LOW
SCL Clock Low Time
T_HIGH SCL Clock High Time
T_SUSTA Setup Time for a Repeated START Condition
T_HDDAT Data Hold Time
T_SUDAT Data Setup Time
T_R
SCL and SDA Rise Time
T_F
SCL and SDA Fall Time
T_SUSTO Setup Time for STOP Condition
NOTES:
1. See Figure 15.
2. Not tested.
3. After this period, the first clock pulse is generated.
4. C_b = the total capacitance of one bus line, in pF.
Std. Mode
Min Max
0 100
4.7
4
4.7
4
4.7
0
250
1000
300
4
Fast Mode
Min
Max
0
400
1.3
0.6
1.3
0.6
0.6
0
0.9
100
20+0.1C_b 300
20+0.1C_b 300
0.6
Units Notes
KHz
µs (1)
µs (1,3)
µs (1,2)
µs (1,2)
µs (1)
µs (1)
ns (1)
ns (1,4)
ns (1,4)
µs (1)
ADVANCE INFORMATION
43