I960 Datasheet, PDF (1/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

ADVANCE INFORMATION
i960^® RP/RD I/O PROCESSOR AT 3.3 VOLTS
• 33 MHz, 3.3 Volt Version (80960RP 33/3.3)
• 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
• Complies with PCI Local Bus Specification Revision 2.1
• 5 Volt PCI Signalling Environment
s High Performance 80960JF Core
s DMA Controller
— Sustained One Instruction/Clock
Execution
— 4 Kbyte Two-Way Set-Associative
Instruction Cache
— 2 Kbyte Direct-Mapped Data Cache
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Programmable Bus Widths:
8-, 16-, 32-Bit
— 1 Kbyte Internal Data RAM
— Three Independent Channels
— PCI Memory Controller Interface
— 32-Bit Local Bus Addressing
— 64-Bit PCI Bus Addressing
— Independent Interface to Primary and
Secondary PCI Buses
— 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
— Direct Addressing to and from PCI
Buses
— Local Register Cache
(Eight Available Stack Frames)
— Unaligned Transfers Supported in
Hardware
— Two 32-Bit On-Chip Timer Units
— Two Channels Dedicated to Primary
s PCI-to-PCI Bridge Unit
— Primary and Secondary PCI Interfaces
— Two 64-Byte Posting Buffers
— Delayed and Posted Transaction
Support
— Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
PCI Bus
— One Channel Dedicated to Secondary
PCI Bus
s I/O APIC Bus Interface Unit
— Multiprocessor Interrupt Management
for Intel Architecture CPUs
(Pentium^® and Pentium^® Pro
Processors)
s Two Address Translation Units
— Dynamic Interrupt Distribution
— Connects Local Bus to PCI Buses
— Multiple I/O Subsystem Support
—
Inbound/Outbound Address Translation
Support
s
I²C Bus Interface Unit
— Direct Outbound Addressing Support
— Serial Bus
— Master/Slave Capabilities
s Messaging Unit
— System Management Functions
— Four Message Registers
— Two Doorbell Registers
s Secondary PCI Arbitration Unit
— Four Circular Queues
— Supports Six Secondary PCI Devices
— 1004 Index Registers
— Multi-priority Arbitration Algorithm
s Memory Controller
— External Arbitration Support Mode
— 256 Mbytes of 32- or 36-Bit DRAM
s Private PCI Device Support
— Interleaved or Non-Interleaved DRAM ^{s SuperBGA* Package}
— Fast Page-Mode DRAM Support
— 352 Ball-Grid Array (HL-PBGA)
— Extended Data Out and Burst
— Extended Data Out DRAM Support
— Two Independent Banks for SRAM / ROM
/ Flash (16 Mbytes/Bank; 8- or 32-Bit)
© INTEL CORPORATION, 1997
September, 1997
Order Number: 273001-002