I960 Datasheet, PDF (3/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
1.0 ABOUT THIS DOCUMENT ....................................................................................................................... 1
1.1 Solutions960^® Program ...................................................................................................................... 1
1.2 Terminology ........................................................................................................................................ 1
1.3 Additional Information Sources ........................................................................................................... 1
2.0 FUNCTIONAL OVERVIEW ....................................................................................................................... 2
2.1 Key Functional Units ........................................................................................................................... 3
2.1.1 PCI-to-PCI Bridge Unit ............................................................................................................. 3
2.1.2 Private PCI Device Support ..................................................................................................... 3
2.1.3 DMA Controller ........................................................................................................................ 3
2.1.4 Address Translation Unit .......................................................................................................... 3
2.1.5 Messaging Unit ........................................................................................................................ 3
2.1.6 Memory Controller ................................................................................................................... 3
2.1.7 I2C Bus Interface Unit .............................................................................................................. 3
2.1.8 I/O APIC Bus Interface Unit ..................................................................................................... 3
2.1.9 Secondary PCI Arbitration Unit ................................................................................................ 4
2.2 i960 Core Features (80960JF) ........................................................................................................... 4
2.2.1 Burst Bus ................................................................................................................................. 5
2.2.2 Timer Unit ................................................................................................................................ 5
2.2.3 Priority Interrupt Controller ....................................................................................................... 5
2.2.4 Faults and Debugging .............................................................................................................. 5
2.2.5 On-Chip Cache and Data RAM ................................................................................................ 5
2.2.6 Local Register Cache ............................................................................................................... 5
2.2.7 Test Features ........................................................................................................................... 5
2.2.8 Memory-Mapped Control Registers ......................................................................................... 6
2.2.9 Instructions, Data Types and Memory Addressing Modes ...................................................... 6
3.0 PACKAGE INFORMATION ....................................................................................................................... 8
3.1 Package Introduction .......................................................................................................................... 8
3.1.1 Functional Signal Definitions .................................................................................................... 8
3.1.2 352-Lead HL-PBGA Package ................................................................................................ 21
3.2 Package Thermal Specifications ...................................................................................................... 31
3.2.1 Thermal Specifications ........................................................................................................... 31
3.2.1.1 Ambient Temperature ............................................................................................... 31
3.2.1.2 Case Temperature .................................................................................................... 31
3.2.1.3 Thermal Resistance .................................................................................................. 31
3.2.2 Thermal Analysis ................................................................................................................... 32
3.3 Sources for Heatsinks and Accessories ........................................................................................... 33
4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 34
4.1 Absolute Maximum Ratings .............................................................................................................. 34
4.2 V_CC5 Pin Requirements (V_DIFF) ........................................................................................................ 34
4.3 Targeted DC Specifications .............................................................................................................. 35
4.4 Targeted AC Specifications .............................................................................................................. 37
4.4.1 Relative Output Timings ......................................................................................................... 39
4.4.2 Memory Controller Relative Output Timings .......................................................................... 39
4.4.3 Boundary Scan Test Signal Timings ...................................................................................... 42
4.4.4 APIC Bus Interface Signal Timings ........................................................................................ 42
4.4.5 I2C Interface Signal Timings .................................................................................................. 43
4.5 AC Test Conditions ........................................................................................................................... 44
4.6 AC Timing Waveforms ...................................................................................................................... 44
4.7 Memory Controller Output Timing Waveforms ................................................................................. 48
5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 55
6.0 DEVICE IDENTIFICATION ON RESET ................................................................................................... 64
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