I960 Datasheet, PDF (11/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
2.2.1 Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960Rx to external memory and peripherals.
The Bus Control Unit fetches instructions and trans-
fers data on the local bus at the rate of up to four 32-
bit words per six clock cycles. The external
address/data bus is multiplexed.
Users may configure the 80960Rx’s bus controller to
match an application’s fundamental memory organi-
zation. Physical bus width is programmable for up to
eight regions. Data caching is programmed through
a group of logical memory templates and a defaults
register. The Bus Control Unit’s features include:
• Multiplexed external bus minimizes pin count
• 32-, 16- and 8-bit bus widths simplify I/O interfaces
• External ready control for address-to-data, data-to-
data and data-to-next-address wait state types
• Little endian byte ordering
• Unaligned bus accesses performed transparently
• Three-deep load/store queue decouples the bus
from the 80960 core
Upon reset, the 80960Rx conducts an internal self
test. Before executing its first instruction, it performs
an external bus confidence test by performing a
checksum on the first words of the Initialization Boot
Record.
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
2.2.4 Faults and Debugging
The 80960Rx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities.
Via software, the 80960Rx may be configured to
detect as many as seven different trace event types.
Alternatively, mark and fmark instructions can
generate trace events explicitly in the instruction
stream. Hardware breakpoint registers are also
available to trap on execution and data addresses.
2.2.5 On-Chip Cache and Data RAM
Memory subsystems often impose substantial wait
state penalties. The 80960Rx integrates consider-
able storage resources on-chip to decouple CPU
execution from the external bus. It also includes a
4 Kbyte instruction cache, a 2 Kbyte data cache and
1 Kbyte data RAM.
2.2.2 Timer Unit
The timer unit (TU) contains two independent 32-bit
timers that are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the Timer Unit registers. These memory-
mapped registers are addressable on 32-bit bound-
aries. The timers have a single-shot mode and auto-
reload capabilities for continuous operation. Each
timer has an independent interrupt request to the
80960Rx’s interrupt controller. The TU can generate
a fault when unauthorized writes from user mode are
detected.
2.2.3 Priority Interrupt Controller
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960Rx exploits several tech-
niques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
ADVANCE INFORMATION
2.2.6 Local Register Cache
The 80960Rx rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register
cache.
2.2.7 Test Features
The 80960Rx incorporates numerous features that
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Rx provides testability features compat-
ible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
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