I960 Datasheet, PDF (25/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
NAME
MA11:0
MWE3:0#
RAS3:0#
Table 8. Memory Controller Signal Descriptions (Sheet 2 of 2)
TYPE
O
R(X)
H(Q)
P(Q)
O
R(1)
H(Q)
P(Q)
O
R(1)
H(Q)
P(Q)
DESCRIPTION
MULTIPLEXED ADDRESS signals are multi-purpose depending on the
device that is selected.
For memory banks 0 and 1, these signals output address bits A13:2. These
address bits are incremented for each data transfer of a burst access.
For DRAM bank, these signals output the row/column multiplexed address
bits 11:0. The relationship between the AD31:0 lines and the MA11:0 lines
depends on the bank size, type and arrangement of the DRAM that is
accessed.
MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH
devices. The MWE’s rising edge strobes valid data into these devices.
MWE0# is asserted for writes to the BE0# lane
MWE1# is asserted for writes to the BE1# lane
MWE2# is asserted for writes to the BE2# lane
MWE3# is asserted for writes to the BE3# lane
ROW ADDRESS STROBE signals are used for DRAM accesses and are
asserted when the MA11:0 signals contain a valid row address. RAS3:0#
always deasserts after the last data transfer in a DRAM access.
Non-Interleaved Operation:
RAS0# = Bank0 access
RAS1# = Bank1 access
RAS2# = Bank2 access
RAS3# = Bank3 access
Interleaved Operation:
RAS0,2# = Even leaf
RAS1,3# = Odd leaf
NAME
DACK#
DREQ#
PICCLK
PICD1:0
Table 9. DMA, APIC, I²C Units Signal Descriptions (Sheet 1 of 2)
TYPE
O
R(1)
H(Q)
P(Q)
I
S(L)
I
I/O
OD
R(Z)
H(Q)
P(Q)
DESCRIPTION
DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this
signal to indicate (1) it can receive new data from an external device or (2) it
has data to send to an external device.
DMA DEMAND MODE REQUEST External devices use this signal to indicate
(1) new data is ready for transfer to the DMA controller or (2) buffers are
available to receive data from the DMA controller.
APIC BUS CLOCK provides synchronous operation of the APIC bus.
APIC DATA lines comprise the data portion of the APIC 3-wire bus.
ADVANCE INFORMATION
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