I960 Datasheet, PDF (47/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 27. BEDO DRAM Output Timings
Symbol
Description
Min
Max Units Notes
T_OV31 RAS3:0# Rising and Falling Edge Output Valid Delay
2
9
ns
2
T_OV32 CAS7:0# Rising Edge Output Valid Delay - Read Cycles 0.5Tc+2 0.5Tc+8 ns
1,2
T_OV33 CAS7:0# Falling Edge Output Valid Delay - Read Cycles
2
8
ns
2
T_OV34 CAS7:0# Rising Edge Output Valid Delay - Write Cycles
2
8
ns
2
T_OV35 CAS7:0# Falling Edge Output Valid Delay - Write Cycles 0.5Tc+2 0.5Tc+8 ns
1,2
T_OV36 MA11:0 Output Valid Delay - Row Address
0.5Tc +2 0.5Tc+10 ns
1,2
T_OV37 MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc +2 0.5Tc+10 ns
1,2
T_OV38 MA11:0 Output Valid Delay - Column Address Write Cycles
2
10
ns
2
T_OV39 DWE1:0# Rising and Falling Edge Output Valid Delay
2
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between V_CC3 maximium and V_SS.
Table 28. SRAM/ROM Output Timings
Symbol
Description
Min
Max
Units Notes
T_OV40
CE1:0# Rising and Falling Edge Output Valid Delay
2
8
ns
2
T_OV41
MWE3:0# Rising Edge Output Valid Delay
1
9
ns
2
T_OV42
MWE3:0# Falling Edge Output Valid Delay
0.5Tc +1 0.5Tc +9
ns
1,2
T_OV43
MA11:0 Output Valid Delay - Initial Address
0.5Tc +2 0.5Tc +10
ns
2
T_OV44
MA11:0 Output Valid Delay - Burst Address
2
10
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between V_CC3 maximium and V_SS.
ADVANCE INFORMATION
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