I960 Datasheet, PDF (43/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
4.4 Targeted AC Specifications
Table 20. Input Clock Timings
Symbol
Parameter
Min Max Units
Notes
T_F
S_CLK Frequency
16 33.33 MHz
T_C
S_CLK Period
30 62.5 ns (1)
T_CS
S_CLK Period Stability
±250 ps Adjacent Clocks (2,3)
T_CH
S_CLK High Time
12
ns Measured at 1.5 V (2,3)
T_CL
S_CLK Low Time
12
ns Measured at 1.5 V (2,3)
T_CR
S_CLK Rise Time
4
V/ns 0.4 V to 2.4 V (2,3)
T_CF
S_CLK Fall Time
4
V/ns 2.4 V to 0.4 V (2,3)
NOTES:
1. See Figure 9.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum
should not have any power peaking between 500 KHz and 1/3 of the S_CLK frequency.
3. Not tested.
Table 21. Synchronous Output Timings
Symbol
Parameter
Min
Max
Units Notes
T_OV1
Output Valid Delay - All Local Bus Signals Except
ALE Inactive and DT/R#
3
15.5
ns (1,2,5)
T_OV2
T_OV3
Output Valid Delay, DT/R#
Output Valid Delay - PCI Signals Except P_REQ#,
S_GNT0#/S_REQ#, and S_GNT5:1#
0.5 T_C +3 0.5 T_C +15 ns (2,5)
2
11
ns (2,5)
T_OV4 Output Valid Delay P_REQ#, S_GNT0#/S_REQ#,
2
and S_GNT5:1#
12
ns (2,5)
T_OV5 Output Valid Delay - DP3:0
3
19
ns (2,5)
T_OF
Output Float Delay
3
13
ns (3,4,5)
NOTES:
1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 39).
2. See Figure 10, TOV Output Delay Waveform (pg. 45).
3. A float condition occurs when the output current becomes less than I_LO. Float delay is not tested, but is designed to be no
longer than the valid delay.
4. See Figure 11, TOF Output Float Waveform (pg. 45).
5. Outputs precharged to V_CC5 maximium.
ADVANCE INFORMATION
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