I960 Datasheet, PDF (18/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
NAME
HOLD
HOLDA
RDYRCV#
W/R#
WIDTH/
HLTD0
12
Table 4. Signal Descriptions (Sheet 4 of 5)
TYPE
I
S(L)
O
R(0)
H(1)
P(Q)
I
S(L)
O
R(0)
H(Z)
P(Q)
I/O
R(H)
H(Z)
P(Q)
DESCRIPTION
HOLD is a request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it
asserts HOLDA, floats the address/data and control lines and enters the T_h
state. When HOLD is deasserted, the processor deasserts HOLDA and
enters either the T_i or T_a state, resuming control of the address/data and
control lines. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration
(pg. 61).
0 = No Hold Request
1 = Hold Requested
HOLD ACKNOWLEDGE indicates to an external bus master that the
processor has relinquished bus control. The processor can grant HOLD
requests and enter the T_h state and while halted as well as during regular
operation. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration (pg.
61).
0 = No Hold Acknowledged
1 = Hold Acknowledged
READY/RECOVER is only used in systems that use an external memory
controller (and do not use the 80960Rx’s memory controller unit). This signal
indicates that data on AD lines can be sampled or removed. When
RDYRCV# is not asserted during a T_d cycle, the T_d cycle extends to the next
cycle by inserting a wait state (T_w).
0 = Sample Data
1 = Do Not Sample Data
RDYRCV# has an alternate function during the recovery (T_r) state. The
processor continues to insert recovery states until it samples the signal
HIGH. This gives slow external devices more time to float their buffers
before the processor drives addresses.
0 = Insert Wait States
1 = Recovery Complete
When using the internal memory controller, connect this signal to V_CC
through a 2.7 KΩ resistor.
WRITE/READ specifies during a T_a cycle whether the operation is a write or
read. It is latched on-chip and remains valid during T_d cycles.
0 = Read
1 = Write
WIDTH denotes the physical memory attributes for a bus transaction in
conjunction with WIDTH/HLTD1/RETRY:
WIDTH/HLTD1/RETRY
WIDTH/HLTD0
0
0
8 Bits Wide
0
1
16 Bits Wide
1
0
32 Bits Wide
1
1
Undefined
WIDTH/HLTD0 For proper operation, do not connect this signal to ground.
This signal has a weak internal pullup which is active during reset to ensure
normal operation.
HLTD0 signal name has no function in the 80960Rx; the signal name is
included for 80960JF naming convention compatibility.
ADVANCE INFORMATION