I960 Datasheet, PDF (45/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
4.4.1 Relative Output Timings
Table 23. Relative Output Timings
Symbol
Parameter
T_LXL
ALE Width
T_LXA
Address Hold from ALE Inactive
T_DXD
DT/R# Valid to DEN# Active
NOTES:
1. Guaranteed by design. May not be 100% tested.
2. See Figure 13.
3. See Figure 14.
4. Outputs precharged to V_CC5 maximium.
Min
0.5T_C-3
0.5T_C-3
0.5T_C-3
Max Units
Notes
ns (1,2,4)
ns Equal Loading (1,2,4)
ns Equal Loading (1,3,4)
4.4.2 Memory Controller Relative Output Timings
Table 24. Fast Page Mode Non-interleaved DRAM Output Timings
Symbol
Description
Min
Max
Units Notes
T_OV6
RAS3:0# Rising and Falling edge Output Valid
2
Delay
9
ns
2
T_OV7
CAS7:0# Rising Edge Output Valid Delay
2
8
ns
2
T_OV8
CAS7:0# Falling Edge Output Valid Delay
0.5Tc+2
0.5Tc+8
ns
1,2
T_OV9
MA11:0 Output Valid Delay-Row Address
0.5Tc+2 0.5Tc+10
ns
1,2
T_OV10
MA11:0 Output Valid Delay-Column Address
2
10
ns
2
T_OV11
DWE1:0# Rising and Falling edge Output Valid
2
Delay
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between V_CC3 maximium and V_SS.
ADVANCE INFORMATION
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