I960 Datasheet, PDF (22/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 2 of 3)
NAME
TYPE
DESCRIPTION¹
P_RST#
I
PRIMARY RESET brings 80960Rx to a consistent state. When P_RST# is
A(L)
asserted:
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as P_SERR# are floated.
• S_RST# asserts.
P_RST# may be asynchronous to S_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
P_SERR#
I/O
OD
R(Z)
PRIMARY PCI BUS SYSTEM ERROR reports address and data parity
errors on the special cycle command, or any other system error where the
result would be catastrophic.
P_STOP#
I/O
R(Z)
PRIMARY PCI BUS STOP indicates that the current target is requesting
the master to stop the current transaction on the primary PCI bus.
P_TRDY#
I/O
R(Z)
PRIMARY PCI BUS TARGET READY indicates the target agent's
(selected device's) ability to complete the current data phase of the trans-
action.
S_AD31:0
I/O
R(0)
SECONDARY PCI ADDRESS/DATA is the secondary multiplexed PCI
address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
S_C/BE3:0#
I/O
R(0)
SECONDARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
S_C/BE3:0# define the bus command. During a data phase, S_C/BE3:0#
are used as byte enables.
S_DEVSEL#
I/O
R(Z)
SECONDARY PCI BUS DEVICE SELECT is driven by a target agent that
has successfully decoded the address. As an input, it indicates whether or
not an agent has been selected.
S_FRAME#
I/O
R(Z)
SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the
beginning and duration of an access on the Secondary PCI bus.
S_GNT0#/
S_REQ#
O
R(Z)
SECONDARY PCI BUS GRANT0 is a grant signal sent to device 0 on the
secondary PCI bus when the internal Secondary PCI Bus Arbiter is
enabled.
SECONDARY PCI BUS REQUEST is the request signal for the 80960Rx
when the arbiter is disabled.
S_GNT5:1#
O
R(Q)
SECONDARY PCI BUS GRANT are grant signals sent to devices 1-5 on
the secondary PCI bus.
S_IDSEL
I
SECONDARY PCI BUS INITIALIZATION DEVICE SELECT selects the
S(L)
80960Rx during a Configuration Read or Write command on the secondary
PCI bus.
S_IRDY#
I/O
R(Z)
SECONDARY PCI BUS INITIATOR READY indicates the initiating agent's
(bus master's) ability to complete the current data phase of the transaction.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
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ADVANCE INFORMATION