I960 Datasheet, PDF (20/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)
NAME
TRST#
VCC
VCC5
VSS
N.C.
VCCPLL3:1
TYPE
I
A(L)
–
–
–
–
I
DESCRIPTION
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor (1.5 KΩ) between this signal and V_SS. When
TAP is not used, this signal must be connected to V_SS; however, no resistor is
required. The signal has a weak internal pullup which must be overcome during reset
to ensure normal operation.
POWER. Connect to a 3.3 Volt V_CC board plane.
5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant
I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V.
When all inputs are from 3.3 V components, connect this signal to 3.3 V.
GROUND. Connect to a V_SS board plane.
NO CONNECT. Do not make electrical connections to these balls.
PLL POWER. For external connection to a 3.3 V V_CC board plane. Power to PLLs
requires external filtering.
Table 6. Interrupt Unit Signal Descriptions
NAME
TYPE
DESCRIPTION
NMI#
S_INT[A:D]#/
XINT3:0#
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
A(L) NMI# is the highest priority interrupt source and is level-detect. When NMI# is
unused, it is recommended that you connect it to V_CC.
I
SECONDARY PCI BUS INTERRUPT¹ requests an interrupt. S_INTx# assertion
A(L) and deassertion is asynchronous to S_CLK. A device asserts S_INTx# when
requesting attention from its device driver. When S_INTx# is asserted, it remains
asserted until the device driver clears the pending request. S_INTx# Interrupts
are level sensitive.
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt
service. These signals operate in dedicated mode, where each signal is assigned
a dedicated interrupt level.
The S_INT[A:D]#/XINT3:0# signals can be directed as follows:
Sec. PCI
S_INTA# ⇒
S_INTB# ⇒
S_INTC# ⇒
S_INTD# ⇒
Primary PCI
P_INTA#
or
P_INTB#
or
P_INTC#
or
P_INTD#
or
80960 Core Processor
XINT0#
XINT1#
XINT2#
XINT3#
XINT7:4#
I
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt
A(L) service. These signals operate in dedicated mode, where each signal is assigned
a dedicated interrupt level.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
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