I960 Datasheet, PDF (10/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
2.1.9 Secondary PCI Arbitration Unit
The Secondary PCI Arbitration Unit provides PCI
arbitration for the secondary PCI bus. It includes a
fairness algorithm with programmable priorities and
six PCI Request and Grant signal pairs. This arbitra-
tion unit can also be disabled to allow for external
arbitration.
2.2 i960 Core Features (80960JF)
The processing power of the 80960Rx comes from
the 80960JF processor core. The 80960JF is a new,
scalar implementation of the 80960 Core Architec-
ture. Figure 2 shows a block diagram of the 80960JF
Core processor.
Factors that contribute to the 80960 family core’s
performance include:
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set-associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
The 80960 core operates out of its own 32-bit
address space, which is independent of the PCI
address space. The local bus memory can be:
• Made visible to the PCI address space
• Kept private to the 80960 core
• Allocated as a combination of the two
S_CLK
PLL, Clocks,
Power Mgmt
TAP _{Boundary Scan}
5
Controller
8-Set
Local Register
Cache
128
Global / Local
Register File
SRC1 SRC2 DST
32-bit buses
Control
address / data
Physical Region
Configuration
Instruction Cache
4 Kbyte Two-Way Set Associative
Bus
Control Unit
Bus Request
Queues
Address/
Data Bus
32
Instruction Sequencer
Constants Control
Multiply
Divide
Unit
Execution
and
Address
Generation
Unit
Effective
Address
Memory
Interface
Unit
32-bit Addr
32-bit Data
Two 32-Bit
Timers
Interrupt
Programmable ^Port
Interrupt Controller 9
Memory-Mapped
Register Interface
1 Kbyte
Data RAM
3 Independent 32-Bit SRC1, SRC2, and DST Buses
2 Kbyte
Direct Mapped
Data Cache
Figure 2. 80960JF Core Block Diagram
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ADVANCE INFORMATION