I960 Datasheet, PDF (15/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
NAME
AD31:0
ADS#
ALE
BLAST#
Table 4. Signal Descriptions (Sheet 1 of 5)
TYPE
I/O
S(L)
R(Z)
H(Z)
P(Q)
O
R(1)
H(Z)
P(1)
O
R(0)
H(Z)
P(0)
O
H(Z)
P(1)
DESCRIPTION
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-
bit data to and from memory. During an address (T_a) cycle, bits 2-31 contain
a physical word address (bits 0-1 indicate SIZE; see below). During a data
(T_d) cycle, read or write data is present on one or more contiguous bytes,
comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations,
unused signals are driven to determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a T_a cycle, specifies
the number of data transfers during the bus transaction on the local bus.
When the DMA or ATUs initiate data transfers, transfer size shown below is
not valid.
AD1 AD0
Bus Transfers
0
0
0
1
1
0
1
1
1 Transfer
2 Transfers
3 Transfers
4 Transfers
When the 80960Rx enters Halt mode and the previous bus operation was:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:2 are driven with the last address value on the AD bus.
Typically, AD1:0 reflect the SIZE information of the last bus transaction
(either instruction fetch or load/store) that was executed before entering Halt
mode.
ADDRESS STROBE indicates a valid address and the start of a new bus
access. The processor asserts ADS# for the entire T_a cycle. External bus
control logic typically samples ADS# at the end of the cycle.
ADDRESS LATCH ENABLE indicates the transfer of a physical address.
ALE is asserted during a T_a cycle and deasserted before the beginning of the
T_d state. It is active HIGH and floats to a high impedance state during a hold
cycle (T_h).
BURST LAST indicates the last transfer in a bus access. BLAST# is
asserted in the last data transfer of burst and non-burst accesses. BLAST#
remains active while wait states are detected via the LRDYRCV# or
RDYRCV# signal on the memory controller. BLAST# becomes inactive after
the final data transfer in a bus cycle. BLAST# has a weak internal pullup
which is active during reset to ensure normal operation when the signal is
not connected.
0 = Last Data Transfer
1 = Not the Last Data Transfer
ADVANCE INFORMATION
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