I960 Datasheet, PDF (26/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
NAME
SCL
SDA
WAIT#
Table 9. DMA, APIC, I²C Units Signal Descriptions (Sheet 2 of 2)
TYPE
I/O
OD
R(Z)
H(Q)
P(Q)
I/O
OD
R(Z)
H(Q)
P(Q)
O
R(1)
H(Q)
P(Q)
DESCRIPTION
I²C CLOCK provides synchronous I²C bus operation.
I²C DATA used for data transfer and arbitration on the I²C bus.
WAIT is an output that allows the DMA controller to insert wait states during
DMA accesses to an external memory system.
NAME
S_CLK
TYPE
I
Table 10. Clock Signal
DESCRIPTION
SYNCHRONOUS PCI BUS CLOCK Provides the processor’s fundamental time
base. All input/output timings are relative to S_CLK.
NAME
ICEADS#
ICEBRK#
ICEBUS7:0
ICECLK
ICELOCK#
ICEMSG#
ICESEL#
ICEVLD#
MSGFRM#
Table 11. ICE Signal Descriptions
TYPE
O
I
I/O
O
I
I
I
O
O
DESCRIPTION
ICE ADDRESS/DATA STATUS indicates a valid address and the start of a new
bus access. ICEADS# is active for accesses to external microcode.
ICE BREAK forces the processor to transition from emulation to interrogation
mode.
ICE BUS is a bidirectional 8-bit bus linking the processor and the emulator.
Used in various modes.
ICE CLOCK output signal to which all ICE bus signals are synchronized.
ICE LOCK is sampled during 80960 core reset to protect ICE configuration.
ICE MESSAGE signal used to acknowledge data from the processor to the
emulator. Used only during interrogation mode.
ICESEL enables or disables the ICE unit.
ICE VALID indicates the processor is driving the ICEBUS with valid data.
ICE MESSAGE FRAME indicates that trace messages are being issued to the
ICEBUS. Used in emulation mode only.
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