I960 Datasheet, PDF (4/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
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i960^® Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2
80960JF Core Block Diagram ........................................................................................................ 4
352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21
352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22
Thermocouple Attachment - No Heat Sink .................................................................................. 31
Thermocouple Attachment - With Heat Sink ................................................................................ 31
VCC5 Current-Limiting Resistor ................................................................................................... 34
AC Test Load ............................................................................................................................... 44
S_CLK, TCLK Waveform ............................................................................................................. 44
T_OV Output Delay Waveform ....................................................................................................... 45
T_OF Output Float Waveform ......................................................................................................... 45
T_IS and T_IH Input Setup and Hold Waveform ............................................................................... 46
T_LXL and T_LXA Relative Timings Waveform ................................................................................. 46
DT/R# and DEN# Timings Waveform .......................................................................................... 47
I²C Interface Signal Timings ........................................................................................................ 47
Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ... 48
Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus . 49
FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States .......................................... 50
FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ........................................... 51
EDO DRAM, Read Cycle ............................................................................................................. 52
EDO DRAM, Write Cycle ............................................................................................................. 52
BEDO DRAM, Read Cycle ........................................................................................................... 53
BEDO DRAM, Write Cycle ........................................................................................................... 53
32-Bit Bus, SRAM Read Accesses with 0 Wait States ................................................................ 54
32-Bit Bus, SRAM Write Accesses with 0 Wait States ................................................................ 54
Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .............. 55
Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................... 56
Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ................................ 57
Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus ........................ 58
Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read,
16-Bit 80960 Local Bus ................................................................................................................ 59
Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit 80960 Local Bus ........................................................................... 60
HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 61
80960 Core Cold Reset Waveform .............................................................................................. 62
80960 Local Bus Warm Reset Waveform .................................................................................... 63
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