I960 Datasheet, PDF (21/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 1 of 3)
NAME
TYPE
DESCRIPTION¹
P_AD31:0
I/O
K(Q)
R(Z)
PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address
and data bus.
P_C/BE3:0#
I/O
K(Q)
R(Z)
PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
P_C/BE3:0# define the bus command. During a data phase, P_C/BE3:0#
are used as byte enables.
P_DEVSEL#
I/O
R(Z)
PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has
successfully decoded the address. As an input, it indicates whether or not
an agent has been selected.
P_FRAME#
I/O
R(Z)
PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning
and duration of an access on the Primary PCI bus.
P_GNT#
I
R(Z)
PRIMARY PCI BUS GRANT indicates to the agent that access to the bus
has been granted. This is a point-to-point signal.
P_IDSEL
I
PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the
S(L)
80960Rx during a Configuration Read or Write command on the primary
PCI bus.
P_INT[A:D]#
O
OD
R(Z)
PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and
deassertion of P_INTx# is asynchronous to S_CLK. A device asserts its
P_INTx# line when requesting attention from its device driver. Once the
P_INTx# signal is asserted, it remains asserted until the device driver
clears the pending request. P_INTx# Interrupts are level sensitive.
P_IRDY#
I/O
R(Z)
PRIMARY PCI BUS INITIATOR READY indicates the initiating agent’s
(bus master’s) ability to complete the current data phase of the transaction.
P_LOCK#
I
PRIMARY PCI BUS LOCK indicates an atomic operation that may require
S(L)
multiple transactions to complete.
P_PAR
I/O
K(Q)
R(Z)
PRIMARY PCI BUS PARITY. This signal ensures even parity across
P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.
P_PERR#
I/O
R(Z)
PRIMARY PCI BUS PARITY ERROR is used for reporting data parity
errors during all PCI transactions except a special cycle.
P_REQ#
O
K(Q)
R(Z)
PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent
desires use of the bus. This is a point to point signal.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
ADVANCE INFORMATION
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