I960 Datasheet, PDF (67/70 Pages) Intel Corporation – i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

i960^® Rx I/O Processor at 3.3 V
S_CLK
Outputs:
AD31:0,
ALE, ADS#, BE3:0#
D/C#/RSTMODE#
LRDYRCV#, FAIL#
WIDTH/HLTD1,
WIDTH/HLTD1/RETRY,
W/R#, DT/R#, DEN#,
BLAST#, LOCK#/ONCE#
HOLD
T_I or T_R
T_H
T_H
T_I or T_A
Valid
Valid
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of S_CLK. HOLDA is granted after the latency counter in the local
bus arbiter expires. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes
HOLD if the last state was T_i or the last T_r of a bus transaction. Similarly, the processor deasserts HOLDA on
the same edge in which it recognizes the deassertion of HOLD.
Figure 32. HOLD/HOLDA Waveform For Bus Arbitration
ADVANCE INFORMATION
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