QG80331M500SL9BE Datasheet, PDF (67/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Documentation Changes
13.
WDTCR also affected by TMR1[3]
Problem:
The developer’s manual specifies in Section 14.4.2.4 that TMRx, bit[3], (where x = 0 or 1) enables
or disables user-mode writes to the timer registers (TMRx, TCRx, TRRx). However, when
TMR1[3] is set, the Watchdog timer register (WDTCR) is also disabled from user-mode writes.
Workaround: TMR1[3] also controls the Watchdog timer.
Affected Docs: Intel^® 80331 I/O Processor Developer’s Manual
14.
Issue:
Workaround:
Split Completion Message clarification
Clarification is required for bridge functionality with split completion message.
Add this to section 2.2.13.3.3 between the second and third paragraph:
“If the split completion message indicates the occurrence of a write-data parity error (i.e. - PCI-X
bridge class and write data parity error index), the bridge asserts PERR# and sets the appropriate
bits in the status register when the transaction completes on the conventional interface. The 80331
bridge exhibits this behavior for both the PCI-X bridge class and completer class transactions.
For all other cases in which a non-posted write transaction completes with a split completion
message, the bridge terminates the transaction on the conventional interface with target abort.”
Affected Docs: Intel^® 80331 I/O Processor Developer’s Manual
15.
Figure 49 in Design Guide shows incorrect trace length
Issue:
Figure 49 in the 80331 Design Guide shows incorrect trace length
Workaround: Figure 49 incorrectly shows the trace length for DQ/DQS/DM as 2.0”-5.0”. The correct trace
length is 2.0”-8.0”, as stated in Tables 58, 59, and 60.
Affected Docs: Intel^® 80331 I/O Processor Design Guide
16.
Issue:
Workaround:
Wrong Voltage Values in Table 21
Table 21 shows wrong voltage values.
Replaced two rows in Table 21. The two rows now appear as follows:
V_OL1
V_OH1
Output Low Voltage (DDR SDRAM)
Output High Voltage (DDR SDRAM)
1.95
0.35
Affected Docs: Intel^® 80331 I/O Processor Datasheet (273943-003).
V
I_OL = 12.5 mA (1, 2)
V I_OH = -12.5 mA (1, 2)
17.
SBR1 Programming When Bank 1 is Unpopulated
Issue:
Section 8.7.6 incorrectly states: “If bank 1 is unpopulated, SBR1[6:0] is programmed either with
all zeroes or a value equal to SBR0[6:0].”
Workaround: The sentence should be changed to “If bank 1 is unpopulated, SBR1[6:0] and SBR1[31:30] should
be programmed with a value equal to SBR0[6:0] and SBR0[31:30].”
Affected Docs: Intel^® 80331 I/O Processor Developer’s Manual
Specification Update
67