QG80331M500SL9BE Datasheet, PDF (15/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Summary Table of Changes
Specification Clarifications
Steppings
No.
Page Status
A-1 B-0 C-x D-0 D-1
Specification Clarifications
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51
No Fix
64 MB and 2 GB DDR333 capacities not to be tested in post-silicon
validation
51 No Fix DDR-II 400 Unbuffered DIMMs are not supported
51 No Fix Interrupt behavior in the 80331 no bridge mode
51 No Fix Memory map for 2 GByte of DDR memory
51 No Fix Back to back MCU MMR reads
52 No Fix Write requirements for the Peripheral Bus Interface
52 No Fix PCI-X Status Register during PCI mode
52 No Fix M_RST# driven to DDR-II or DDR-I voltage levels
52 No Fix BIU master abort causes two interrupts on reads.
53 No Fix Reset Internal Bus (PCSR.5) usage
53 No Fix No Bridge Mode (BRG_EN) validation
53 No Fix Potential race condition with Interrupt Controller Unit status bits
54 No Fix Bus Interface Unit follows PCI ordering rules
55
No Fix
UART, I²C and GPIO memory mapped registers should be
addressed with 32-bit accesses
55 No Fix Flash Wait States
55 No Fix UART Interrupt Identification Register
55 No Fix Reads on 16-bit PBI bus operate as 32-bit
56 No Fix Embedded Design Usage Model - Secondary PCI bus only
56 No Fix 3.3 V to 1.5 V leakage
56 No Fix Accessing “reserved” registers in “no bridge” mode
56 No Fix Power plane isolation for Battery Back-Up (BBU) mode
57 No Fix AAU result can be written directly to PCI host memory
57 No Fix PWRDELAY functionality during power sequencing
57 No Fix PBI lockout condition
57 No Fix Interleaving descriptors with D-0 AAU
58 No Fix RCVDLY setting for DDR-I memory
58 No Fix ATUBAR3 Functionality
58 No Fix VREF isolation for Battery Back-up (BBU) mode
58 No Fix I2C Unit Enabling
59
No Fix
DMA transactions from local memory to a conventional PCI target
can complete out of order
59 No Fix SBR1 Programming with Bank 1 Unpopulated
59
No Fix
32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit
Aligned Writes
60
Fixed Case Temperature Clarification.
Specification Update
15