QG80331M500SL9BE Datasheet, PDF (49/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Specification Changes
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Update - These routing guidelines were added to the October 2004 release of the 80331 design
guide (273823-002)
Intel® 80331 I/O Processor Design Guide change for PCI/-X busses
The latest routing guidelines for the PCI/-X busses are available upon request and included in the
next revision of the Intel^® 80331 I/O Processor Design Guide.
Update - These routing guidelines were added to the October 2004 release of the 80331 design
guide (273823-002)
Internal bus operates at 333 MHz for D-0 stepping
For the D-0 stepping of the 80331, the internal bus operates at 333 MHz. For all previous
steppings, the internal bus runs at 266 MHz.
Application Accelerator Unit enhanced for D-0 stepping
The Application Accelerator Unit (AAU) in the D-0 stepping has been enhanced to support RAID
6 functionality. The details of this new feature are described in an addendum to the AAU chapter.
Recommended DLL register values
Using the default DLL values in combination with low duty cycle DIMMs may result in low hold
time margins on read transactions.
The default values for the DLL master and slave registers do not center the internal DQS with
respect to the eye of the incoming data. Using the default values may result in a reduced hold time
due to DQS being late in the data eye, which could lead to ECC errors. Errors have only been
observed when using DIMMs that have a low DQS duty cycle.
Note: All of the Intel validation up to this point has been with the default, worst case DLL values
and all DIMMs used in validation have passed.
Firmware should be updated and tested with these new DLL values, in order to add margin to the
hold timing during memory reads.
DDR-II 400 settings
SLVLMIX0 - Address FFFF_F554h; Recommended value - 3333_3333h
SLVLMIX1 - Address FFFF_F558h; Recommended value - 0000_0003h
SLVHMIX0 - Address FFFF_F55Ch; Recommended value - 3333_3333h
SLVHMIX1 - Address FFFF_F560h; Recommended value - 0000_0003h
SLVLEN - Address FFFF_F564h; Recommended value - 0000_0003h
MASTMIX - Address FFFF_F568h; Recommended value - 0000_000Ah
MASTLEN - Address FFFF_F56Ch; Recommended value - 0000_0002h
DDR-I 333 settings
SLVLMIX0 - Address FFFF_F554h; Recommended value - 6666_6666h
SLVLMIX1 - Address FFFF_F558h; Recommended value - 0000_0006h
SLVHMIX0 - Address FFFF_F55Ch; Recommended value - 6666_6666h
SLVHMIX1 - Address FFFF_F560h; Recommended value - 0000_0006h
SLVLEN - Address FFFF_F564h; Recommended value - 0000_0003h
MASTMIX - Address FFFF_F568h; Recommended value - 0000_0000h
MASTLEN - Address FFFF_F56Ch; Recommended value - 0000_0002h
DDR-II JEDEC initialization sequence includes writes to EMRS2 and EMRS3
The JEDEC DDR-II specification includes a write to EMRS2 and EMRS3 (Extended Mode
Register Set) during the initialization sequence. Step 5 is ‘Issue EMRS2 command’ and step 6 is
Specification Update
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