QG80331M500SL9BE Datasheet, PDF (35/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
48.
Problem:
Bridge PCI ordering rule violation
When the bridge is in PCI-to-PCI mode, it receives a downstream memory write which is claimed
by the bridge, followed by a subsequent memory read request which is enqueued immediately
afterwards. At the same time, the upstream buffers on the chip are filled with upstream Memory
Writes and read completion data. On the destination bus, the memory write is issued in small
fragments due to either target disconnect or a low setting of the secondary MLT, and the upstream
buffers begin to free up due to delivery of upstream Memory Write data. In between delivery of
downstream Memory Write fragments, the bridge issues the subsequent Memory Read, in violation
of PCI ordering rules.
Implication:
Summary of the four failure modes:
1. PCI-to-PCI: A Memory Read transaction may pass a previously enqueued Memory Write.
2. PCI-to-PCI: A Configuration or I/O Read transaction may pass a previously enqueued
Memory Write.
3. PCI-to-PCI: A Configuration or I/O Write transaction (including type1 configure-to-special
cycle) may pass a previously enqueued Memory Write.
4. PCI-X-to-PCI: A Configuration or I/O Write transaction (including type1 configure-to-special
cycle) may pass a previously enqueued Memory Write.
In the above scenario, a PCI read/write transaction can pass a PCI memory write transaction which
violates PCI ordering rules.
Workaround:
Status:
When the primary bus is PCI and secondary bus is PCI-X, this would only be seen as described in
item 4 listed above. No impact when the bridge is configured in PCI-X to PCI-X mode.
Use in PCI-X to PCI-X mode. When the primary bus is PCI and secondary bus is PCI-X, do not use
upstream DWORD I/O or type1 configure-to-special cycle writes that must be ordered against
previously issued Memory Writes.
Fixed. Fixed in D-0 stepping. See the Table , “Summary Table of Changes” on page 9.
49.
Problem:
ATU claims PCI commands 8 and 9 when issued as Dual Address Cycle
(DAC)
In PCI mode, commands 8 and 9 are reserved. The appropriate PCI response to these commands is
to master abort. When these commands are issued as a Dual Address Cycle (DAC), the Address
Translation Unit (ATU) claims them and they are executed as Memory Read (command 8) and
Memory Write (command 9) on the internal bus. The ATU properly master aborts SAC PCI
commands 8 and 9.
Implication:
Workaround:
Status:
This issue does not occur in PCI-X mode.
No negative impact expected, since these PCI commands are ‘reserved’ and should not be issued to
the ATU.
No workaround.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
Specification Update
35