QG80331M500SL9BE Datasheet, PDF (52/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Specification Clarifications
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Write requirements for the Peripheral Bus Interface
PBI write requirements are:
• must set up the Flash or memory to accept writes.
• must ensure the write has occurred before another one starts.
• it is illegal to burst writes to the PBI.
The data presented should not be larger than the PBI width.
Any PBI device should be mapped in the MMU the same. Making the device address space
cachable can result in buffered/coalesced writes, which are burst to the PBI. XCB=000 and
XCB=001 are the only cache policies that should be used for PBI. All other cache policies result in
multi-byte transactions.
No Fix. See the Table , “Summary Table of Changes” on page 9.
PCI-X Status Register during PCI mode
The PCI-X Status Register (PX_SR, offset E4h-E5h) in the ATU has meaning only in PCI-X mode.
The device number and bus number fields are always updated when a configuration write is
detected. The ATU always grabs AD[15:11] for configuration writes, whether it is in PCI or PCI-X
mode. When a PCI configuration transaction occurs, the Device Number bits (7:3) are updated to a
value of “00000” from the default value of “11111”. The bus number bits (15:8) are only grabbed
during the attribute phase (which does not exist for PCI).
No Fix. See the Table , “Summary Table of Changes” on page 9.
M_RST# driven to DDR-II or DDR-I voltage levels
The de-asserted voltage level on M_RST# with DDR-II is 1.8 Volts and with DDR-I is 2.5 Volts.
When M_RST# is needed for other devices (i.e,. - Flash), make sure these voltage levels are
appropriate for the target device.
No Fix. See the Table , “Summary Table of Changes” on page 9.
BIU master abort causes two interrupts on reads.
The B-0 stepping added a Bus Interface Unit (BIU) interrupt when the BIU gets master aborted on
an internal bus write (see erratum #8). The functionality is different between a read and write case.
For a write, the BIU master abort asserts IINTSRC.29 (when enabled) and does not assert an error
to the core. For a read, the BIU master abort asserts both IINTSRC[29] (when enabled) and an
error to the core. Therefore, on a read case two interrupts is generated. When the interrupt source is
masked, then only the master abort on reads is detected, and this is from the direct core error.
No Fix. See the Table , “Summary Table of Changes” on page 9.
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Specification Update