QG80331M500SL9BE Datasheet, PDF (34/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
47.
Problem:
Implication:
VCCDDR (VCC25/VCC18) Current Spike
An internal DDR signal gets routed through logic that is powered by the VCC15 rail. This signal
gets driven to the wrong level when VCC15 rail is not powered up. This signal controls the input
and output enable of all DDR buffers, so when VCC15 is off and VCC25/18 is on, it asserts high
and cannot tristate the DDR outputs. The issue can occur at power-up, power down and power fail
when battery back-up continues to power the 80331.
Excessive VCC25/18 power supply rail current to the VSS rail is experienced until VCC15 core
supply is up.
Also, when using DDR-I mode (VCC25), the buffers can be overstressed when VCC15 = off and
VCC25 = on. This can cause a reliability problem since the processor may become damaged over
time.
Workaround:
When in DDR-II mode (VCC18), the buffers do not overstress since VCC18 maximum is 1.9 V.
Therefore, no reliability problems exist.
A new power sequencing requirement should be followed for B-0 and C-0 steppings. This problem
does not affect A-1 stepping, and is being fixed in C-1 stepping.
1. VCC33 power up
2. VCC15 power up
3. VCC25/18 power up
The VCC15 minimum supply voltage has to be within 25% of the VCC25 supply voltage, until the
VCC15 supply reaches 1.425 V (VCC15 minimum), during power-up and power-down sequences.
This is the minimum requirement to ensure no gate overstress when using DDR-I memory.
Status:
For power-fail condition, the battery should power only the DIMM. The 80331 should be isolated
from the battery power.
Fixed. Fixed in C-1 stepping. See the Table , “Summary Table of Changes” on page 9.
34
Specification Update