QG80331M500SL9BE Datasheet, PDF (55/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Specification Clarifications
Status:
14.
Issue:
Status:
15.
Issue:
Status:
16.
Issue:
Status:
17.
Issue:
No Fix. See the Table , “Summary Table of Changes” on page 9.
UART, I²C and GPIO memory mapped registers should be addressed with
32-bit accesses
The UART, I²C and GPIO units sit on a dedicated low speed internal bus that does not support byte
enables. Due to this functionality, accessing any of these unit memory mapped registers (MMR)
with any accesses less than 32-bits can result in corruption of the other bits in the 32-bit MMR. For
example, beginning with C-0 stepping, the GPOD register (located at FFFF_F788h) added new bit
functions to bits 10 and 11. When software does a byte access to GPOD, this could cause bits 10
and 11 to be written with incorrect data.
While most of these registers only implement the lower 8-bits (the upper three bytes are
‘reserved’), the recommendation is that all UART, I²C and GPIO MMRs should only be accessed
as 32-bit registers. While it is desired that 32-bit accesses be performed, it is acceptable to access
with less than 32-bits, as long as all non-reserved bits are accessed. For purposes of future
expansion, 32-bit accesses are preferred.
No Fix. See the Table , “Summary Table of Changes” on page 9.
Flash Wait States
The Address-to-Data wait state and Recovery Cycle wait state fields in Table 60 (PBBAR0) and
62 (PBBAR1) are incorrect in the Intel^® Lindsay I/O Processor Component Specification,
Rev. 2.0, Vol. 2. The Address-to-Data wait state is actually one more than listed, and the Recovery
Cycle wait state is actually two more than listed. See Documentation Change # 8 for more specific
information.
No Fix. See the Table , “Summary Table of Changes” on page 9.
UART Interrupt Identification Register
The UART Interrupt Identification Register (UxIIR) is read by software to determine the type and
source of UART interrupts. This register gathers and priority encodes the various sources of UART
interrupts. The register is read after an interrupt occurs. Enabling and disabling of interrupts (via
the Interrupt Enable Register - UxIER or Modem Control Register - UxMCR) effects whether or
not the interrupt to the processor occurs. This does not effect the logging of the status of what is
happening in the UART. The UART operates in interrupt or polling mode. In polling mode, all
interrupts to the processor would be disabled.
No Fix. See the Table , “Summary Table of Changes” on page 9.
Reads on 16-bit PBI bus operate as 32-bit
2-byte and 4-byte read transactions on the Peripheral Bus Interface (PBI) bus operate as burst reads
(in other words, two 16-bit read cycles). All the read transactions from the Intel XScale^® core to
PBI devices (in other words, SRAM, Flash, etc.) are translated to burst reads with burst size of 2,
even though there is no necessity to generate a burst transaction. Therefore, devices on the 16-bit
PBI bus should be configured as pre-fetchable.
Note: 1-byte transactions on 16-bit PBI bus is not a supported case. Also, a PBI bus configured as 8-bit
does not operate this way.
Status:
No Fix. See the Table , “Summary Table of Changes” on page 9.
Specification Update
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