QG80331M500SL9BE Datasheet, PDF (28/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
35.
Problem:
Implication:
Workaround:
Status:
I²C unit hang condition
When a processor reset occurs, the 80331 does not properly detect an idle condition on the I²C bus,
potentially causing the I²C unit to hang indefinitely. This occurs only when an I²C slave device is
writing a 0 on the SDA signal when reset is asserted. The SCL signal goes high, but SDA remains
low, signaling that the bus is still busy. Warm reset does not clear up this condition; only a cold
reset (power-on) resolves the I²C bus hang.
The I²C bus stays in a hang condition indefinitely
Since this is fixed in the C-0 stepping, this workaround must be implemented only when I²C hang
issues are preventing proper usage of A-2 and B-0 parts. The recommended workaround for A-1
and B-0 parts involves both a hardware and software change. In hardware, tie GPIO pins to the
SCL signals; then in the initialization software, the GPIO pins must toggle the SCL signals to bring
the slave I²C devices out of the locked condition. This can be done by using one GPIO signal and
an external tristate buffer on SCL lines, or by using two GPIO signals and no external logic to
allow unlocking the I²C bus. Also, the external PWRDELAY circuit must use S_RST#, instead of
PWRGD.
Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.
In the C-0 stepping, the I²C bus lock condition can be cleared by software doing a toggle of the
GPOD[11:10] to toggle SCL[1:0]. Bit[11] and bit[10] of the GPOD register are writable. When
GPOD[11] is high, SCL[1] is driven low. When GPOD[10] is driven high, SCL[0] is driven low.
I²C is no longer in the processor reset equation for the internal bus (that it, MRST), so the I²C bus
can hang when a reset happens during the reading of a 0 from an external I²C slave. Therefore, the
software is required to toggle the I²C clock signals (at least eight times) before I²C is enabled.
GPOD bit[11] and bit[10] can be used to unhang the bus by creating a 100 K (5 ms high and low
time) or 400 K (1.25 ms high and low time) clock pulse.
Also, since the I²C bus has been removed from the processor reset equation, the PWRDELAY
circuit is no longer needed. Only a 1.5 KΩ pull-up to 3.3 V is required on PWRDELAY. See
Specification Change 11, “PWRDELAY needs only a pull-up for battery back-up mode” on
page 48.
36.
Problem:
Implication:
Workaround:
Status:
VPD Data Register bit 19 is not read/write
VPD (Vital Product Data) is an extended capability of the ATU. Bit 19 of the VPD Data Register
(FFFF_E1BCh) was implemented as RC (read clear) instead of RW (read/write).
This is application dependant as VPD provides the system with information that uniquely identifies
hardware and, potentially, software elements of a system.
When the VPD feature is needed, care must be taken to mask bit 19.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
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Specification Update