QG80331M500SL9BE Datasheet, PDF (36/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
50.
Problem:
Secondary bus PCI RST# pulse prior to the rising edge of P_RST#
During system power on and prior to 80331 receiving the rising edge of P_RST#, a pulse may be
observed on the secondary bus PCI RST# signal (S_RST#).
Implication:
Workaround:
This functionality is a result of the 3.3v to 1.5v leakage described in Specification Clarification 19.
Other signals that may see a pulse during power-on include the following: all Peripheral Bus
Interface (PBI), PCI, GPIO, UART, JTAG and PWRDELAY signals. Refer to Specification
Clarification 23 for specifics on PWRDELAY. Signals not included are DDR and I2C.
PCI/PCI-X controllers on the secondary bus segment could interpret this S_RST# pulse as a true
rising edge and initialize into an undetermined state. Pulses on PWE# and PCEx# may cause data
corruption for memory devices connected to the PBI bus.
A hardware workaround has been identified. The P_RST# signal that is received by the 80331 can
be used to gate the secondary bus PCI RST# signal. For example, use P_RST# and S_RST# as
inputs to an AND gate and connect the output to the secondary device RST# pin. The gate delay
should be kept down to a couple nanoseconds, so as to not interfere with the PCI initialization
pattern.
Status:
Another workaround is to bring up 3.3 V and 1.5 V power rails simultaneously, but continue to
maintain the power sequencing requirement (as specified in the design guide) for these two power
rails.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
51.
Problem:
Implication:
Workaround:
Slow edge rates observed when 80331 is driving the primary bus
Signal integrity issues might occur when the 80331 is driving the primary PCI/PCI-X bus in
conventional PCI or PCI-X modes.
Parity errors and system hangs may occur.
A software workaround has been identified. The workaround is required for reliable conventional
PCI and PCI-X mode operation. The workaround is to write all 1s to the PCI drive strength
overrides with the Intel XScale^® core.
Status:
Bit 31 should be set in the following two registers to enable drive strength override:
• 3.3 V Drive Strength Control Register at FFFF_F5D0h
• 1.5 V Drive Strength Control Register at FFFF_F5D4h
The default value is 0000_3F3Fh for both registers.
Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.
36
Specification Update