QG80331M500SL9BE Datasheet, PDF (26/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
27.
Problem:
Implication:
Workaround:
Status:
SERR# set to incorrect voltage
SERR# is being driven to 1 V. The 80331 might detect SERR# being asserted during boot-up and
does not detect SERR# assertion when a device on the PCI-X bus asserts SERR#.
The 80331 falsely detects and logs SERR# assertion during boot-up, due to the SERR# pin being
held at 1 V, which the 80331 detects as a logic low (asserted). Devices assert SERR# for a
minimum of one clock when an SERR# occurs. Since SERR# is being held low, devices asserting
SERR# are not detected by the 80331.
Putting a 34–39 Ω pull-up resistor on SERR# might work; however, some add-in cards do not have
the drive strength to pull-down against this pull-up, and therefore cannot reliably generate SERR#
in the system. An alternative workaround is to have software mask SERR# assertion in the ATU or
bridge.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
28.
Problem:
Implication:
Workaround:
Status:
M66EN set to incorrect voltage
The M66EN signals do not get set to the appropriate level with or without an add-in card present.
M66EN should be at 3.3 V without an add-in card present.
Prevents auto-detection of 66 MHz PCI devices. Forces the bus speed to 33 MHz when not in
PCI-X mode and only impacts busses that should be set to 66 MHz PCI.
Use a 34-39 ohm pull-up resistor on the M66EN signals.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
29.
Problem:
Implication:
Workaround:
Status:
P_INT[D:A]# not operating correctly
The P_INT[D:A]# signals only rise to ~1 V at power-on.
P_INT[D:A]# interrupt signals can cause false interrupts to the host.
Use a 34-39 ohm pull-up resistor on the P_INT[D:A]# signals.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
30.
Problem:
Implication:
Workaround:
Status:
Secondary bus may not initialize correctly at 100 MHz PCI-X or 133 MHz
PCI-X
When a 133 MHz PCI-X capable device is plugged into the secondary PCI-X bus supporting
>= 100 MHz PCI-X, the 80331 might not correctly initialize the bus at 100 MHz PCI-X or
133 MHz PCI-X.
The bus may initialize at 66 MHz PCI-X.
Replace the 3.3 Kohm pull-up resistor on S_PCIXCAP with a 1.5 Kohm resistor.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
31.
Problem:
Implication:
Workaround:
Status:
Coalesced writes to 32-bit memory can cause data corruption
The Bus Interface Unit (BIU) can cause data corruption within the memory controller unit when
either an 8-byte write with a starting address offset of four (i.e., DWord alignment) or a 12-byte
write is done to 32-bit memory (or the 32-bit memory region).
Can cause data corruption. This is not an issue with 64-bit memory subsystems.
When the use of 32-bit memory or the 32-bit memory region is required, write coalescing must be
turned off.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
26
Specification Update