QG80331M500SL9BE Datasheet, PDF (66/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Documentation Changes
10.
Problem:
Power sequence timing
Section 9.1 of the Intel^® 80331 I/O Processor Design Guide describes the power sequence
requirement between VCC33 and VCC15, but does not mention any timing parameters.
Workaround: The following are the power sequencing requirements that must be followed:
1. The 80331 requires that the VCC33 voltage rail be no less than 0.5 V below VCC15 (absolute
voltage value) at all times during operations, including during system power-up and
power-down. In other words, the following must always be true:
— VCC33 >= (VCC15 - 0.5 V). This can be accomplished by placing a diode (with a voltage
drop < 0.5 V) between VCC15 and VCC33. The Anode is connected to VCC15 and the
Cathode is connected to VCC33.
2. When a voltage regulator solution is used, which shunts VCC15 to ground while VCC33 is
powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is
fully powered is 20 ms.
3. The maximum allowed time between VCC33 and VCC15 ramping is 525 ms. There is no
minimum sequencing time requirement.
Affected Docs: Intel^® 80331 I/O Processor Design Guide
11.
Updated Peripheral Bus Interface (PBI) timings
Problem:
Table 27 in the 80331 datasheet must be updated.
Workaround: Table 27 must have the following values:
• Tah1 – ALE high time = 15 ns minimum
• Tav1 – ALE high to address valid = 0 ns maximum
• Tah2 – ALE low to address invalid = 15 ns maximum
• Tas1 – Address valid to ALE low = 15 ns minimum
• Tao1 – ALE low to POE# low = 0 ns minimum
• Taw1 – ALE low to PWE# low = 15 ns minimum
• Tah3 – PWE# high to data invalid = 15 ns minimum
• Tas2 – Data valid to PWE# high = 6 0ns minimum
• Tac1 – ALE low to PCE[1:0]# low = 15 ns minimum
Affected Docs: Intel^® 80331 I/O Processor Datasheet
12.
ATU PM_CAP[5] text must be updated
Problem:
Table 140, bit[5] reads as follows: DSI – This field is set to 0₂ meaning that this function requires a
device specific initialization sequence following the transition to the D0 uninitialized state.
Workaround: It must be changed to the following: DSI – This field is set to 0₂ meaning that this function does not
require a device specific initialization sequence following the transition to the D0 uninitialized
state.
Affected Docs: Intel^® 80331 I/O Processor Developer’s Manual
66
Specification Update