QG80331M500SL9BE Datasheet, PDF (39/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
55.
Problem:
Implication:
No support for burst I/O and configuration read/writes
The 80331 bridge does not support burst I/O read, I/O write, configuration read, or configuration
write in PCI mode.
In conventional PCI mode, it is legal for a requester to attempt a burst I/O read, I/O write, configu-
ration read, or configuration write. The 80331 bridge supports only single data phase configuration
and I/O transactions.
When a master attempts to issue a burst I/O or configuration read, the bridge does not assert
STOP# after the first data phase, resulting in data corruption of all DWords beyond the first.
For burst I/O or configuration writes, the bridge asserts STOP#, but does not de-assert TRDY# on
the final data phase, resulting in loss of data (the second data phase is dropped by the bridge).
Workaround:
Status:
PCI-X does not permit these modes of operation.
X86 processors do not allow this condition to occur. In non-X86 systems that do not preclude these
burst mode operations, the application must limit the transfer to a single aligned DWORD (32 bit)
operation.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
56.
Problem:
Implication:
Workaround:
Status:
Read flow through hangs due to disconnect without data at a buffer
boundary.
Read flow through hangs due to disconnect without data at a buffer boundary.
In PCI to PCI mode an upstream read is issued to the bridge and forwarded to the primary bus,
using a calculated prefetch size of at least 3 cachelines. On the primary bus, the target claims the
request, and delivers data (with intermittent TRDY# slips) up to a 128-byte boundary, then
deasserts TRDY# and waits a number of clocks before disconnecting without data. After the 2nd
chatelaine gets on chip, the bridge enters flow-through and begins delivering data to the initiator. If
the time difference between the end of the primary bus read and the end of the secondary bus read
is approximately 10 clocks or less, the bridge may hang after the data is delivered.
PCI-X to PCI-X and PCI to PCI-X implementations are not affected by this issue.
For PCI to PCI systems in which targets might exhibit the above behavior, set all prefetch factors to
000b. This will set the maximum prefetch size to 2 cachelines (for MRM) and effectively disable
read flow-through. There may be a performance impact due to these settings.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
57.
Problem:
Implication:
Workaround:
Status:
P_SERR# not asserted for parity error on AD[63:32]
Primary side P_SERR# is not asserted for a parity error on AD[63:32] during the data phase of a
split response to a read request issued by the bridge.
Since no valid data is driven onto the upper A/D bus during a split response for a read transaction,
there are no negative side affects of not asserting P_SERR# in this case.
This behavior does not comply with the PCI-X specification v1.0a requirements in section 5.4.1.3,
however it will have no impact in the application.
No workaround needed.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
58.
Problem:
Bus Interface Unit (BIU) claims DAC addresses in the range of the Memory
Mapped Registers (MMR
The BIU incorrectly decodes and claims Dual Address Cycle (DAC) addresses in the
xxxx_xxxx_FFFF_E000h to xxxx_xxxx_FFFF_FFFFh range (e.g. - ‘x’ represents any bit being set
Specification Update
39