QG80331M500SL9BE Datasheet, PDF (13/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Summary Table of Changes
Core Errata
Steppings
No.
Page Status
A-1 B-0 C-0 D-0 D-1
Errata
1
XXXX
X
43 No Fix Abort is missed when lock command is outstanding
2
XXXX
X
43
No Fix
Aborted Store that Hits the Data Cache May Mark Write-Back
Data as Dirty
3
XXXX
X
44
No Fix
Performance Monitor Unit event 0x1 can be incremented
erroneously by unrelated events
4
XXXX
X
44
No Fix
In Special Debug State, back-to-back memory operations —
where the first instruction aborts — may cause a hang
5
XXXX
X
45
No Fix
Accesses to the CP15 ID register with opcode2 > 0b001
returns unpredictable values
6
XXXX
X
45
No Fix
Disabling and re-enabling the MMU can hang the core or
cause it to execute the wrong code
7
XXXX
X
46
No Fix
Updating the JTAG parallel registers requires an extra TCK
rising edge
8
XXXX
X
46
No Fix
Non-branch instruction in vector table may execute twice after
a thumb mode exception
Specification Update
13