QG80331M500SL9BE Datasheet, PDF (64/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Documentation Changes
Table 236. DDR SDRAM Control Register 0 - SDCR0 (Sheet 2 of 2)
IOP
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rv rw rw rw rv rw rw rw rv rv rw rw rv rv rw rw rv rv rw rw rv rv rw rw rv ro rw rw
PCI
Attributes ^{na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na}
Intel XScale^® core Local Bus Address
FFFF E504H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:06
05:04
03
02
01
00
002
Reserved.
ODT Termination Value: Determines the termination value of the On Die Termination for both Banks
(controlled by ODT[1:0]). Applies to DDR-II SDRAM memory type only.
• 00 Disabled
002
• 01 75 ohm
• 10 150 ohm
• 11 reserved
02
Varies with
external state
of
MEM_TYPE
at PCI bus
reset
Reserved
DDR Type: Identifies the selected DDR generation of SDRAM based on the MEM_TYPE reset strap.
0 = DDR-II (supported speed of 400 MHz) - MEM_TYPE Deasserted.
1 = DDR (supported speed of 333 MHz) - MEM_TYPE Asserted.
Data Bus Width: Indicates the width of the data bus. See Section 8.3.3.4, “32-bit Data Bus Width” on
page 458.
02
0 = 64 bits
1 = 32 bits
DIMM Type: Selects unbuffered or registered DIMM operating modes for the MCU.
02
0 = Unbuffered*
1 = Registered
NOTE: Unbuffered DDR SDRAM memory subsystems will use the Unbuffered mode.
64
Specification Update