QG80331M500SL9BE Datasheet, PDF (14/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Summary Table of Changes
Specification Changes
Steppings
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A-1 B-0 C-x D-0 D-1
Specification Changes
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47
Doc HPI# (High Priority Interrupt) is a maskable interrupt
47
Doc PCIODT_EN Reset Strap Signal
47
Doc LOCK# functionality has been de-featured
47
Doc Watchdog Timer and Retry Timer has been de-featured
47
Doc
P_GNT# and P_REQ# signals have new ball locations on
B-0
47
Doc Peripheral Performance Monitor Unit has been de-featured
48
Doc Processor Device ID has been removed
48
Doc 1.5K pull-down required on AD[15] of the PBI bus
48
Doc OCD and Receive Enable calibration de-featured
48
Doc New Watchdog Timer (WDT) functionality in B-0 stepping
48
Doc PWRDELAY needs only a pull-up for battery back-up mode
48
Doc ARB_EN signal has been de-featured
48
Doc
Intel® 80331 I/O Processor Design Guide change for
Unbuffered DDR-I dual-banked DIMMs
48
Doc
DDRRES2 can be pulled down to reduce current during
self-refresh
48
Doc
Intel® 80331 I/O Processor Design Guide change for
Peripheral Bus Interface (PBI)
49
Doc
Intel® 80331 I/O Processor Design Guide change for
PCI/-X busses
49
Doc Internal bus operates at 333 MHz for D-0 stepping
49
Doc Application Accelerator Unit enhanced for D-0 stepping
49
Doc Recommended DLL register values
49
Doc
DDR-II JEDEC initialization sequence includes writes to
EMRS2 and EMRS3
50
Doc Case temperature (Tcase) change
50
Fixed Internal Clock Misalignment.
14
Specification Update