QG80331M500SL9BE Datasheet, PDF (38/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
53.
Problem:
Implication:
PCI-to-PCI read flow-through with destination TRDY# stalls can cause data
corruption
PCI-to-PCI read flow-through with destination TRDY# stalls can cause data corruption.
The scenario is a PCI-to-PCI memory read with flow-through enabled (source bus bandwidth is
less than or equal to destination bus bandwidth). Requestor initiates the read on the source bus, and
it is retried by the bridge (executed as a delayed transaction). The bridge plays the transaction on
the destination bus and starts receiving data from the target. After getting two or three cache lines,
the transaction is requested again on the source bus, and the bridge enters flow-through. The target
device on the destination bus begins to insert target wait-states, and eventually ends the transaction
by stalling TRDY# for a number of clocks then signaling disconnect without data at the cache line
boundary. On the source bus, the bridge delivers an extra garbage dataphase beyond what was
received on the destination side, causing data corruption.
Workaround:
The affected mode is PCI-to-PCI only. Neither PCI-X-to-PCI-X nor PCI-to-PCI-X modes allow
TRDY# stalls on the destination side.
Do not use in PCI-to-PCI configuration. Expected usage model for the 80331 is that the secondary
PCI bus operates in PCI-X mode only.
For an alternate workaround, when in a system that has devices that might terminate transactions in
the above manner, the prefetch policy registers must be set so that the target is not given the
opportunity to significantly stall TRDY#.
Status:
For example: When a device can provide 256 bytes in a timely manner, but delays a request for 384
bytes, the first read and reread factors must not be set higher than 01h (giving an MRM prefetch of
256 bytes, assuming a 64-byte cache-line size).
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
54.
Problem:
Implication:
Workaround:
Status:
S_PCIXCAP PCI mode threshold is too high
The “PCI mode” threshold on the S_PCIXCAP signal on the secondary PCI bus is too high
(1.87 V). This has the effect of detecting a PCI bus when more than two slots are populated with
PCI-X 66 cards.
A heavily loaded secondary PCI bus (three or four slots), might operate in PCI mode instead of
PCI-X mode.
When a board is configured with more than two PCI-X slots, a circuit can be added to adjust the
PCIXCAP voltage.
Fixed. Fixed in D-0 stepping. See the Table , “Summary Table of Changes” on page 9.
38
Specification Update