QG80331M500SL9BE Datasheet, PDF (41/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
60.
Problem:
Implication:
Workaround:
Status:
Tc1(min) of the PCI-X clock observed to be marginally less than the
requirement specified for the PCI-X (Mode 1, class1) clock jitter.
The 80331 generates the PCI-X clock with a nominal frequency of 133 MHz (Tc1 of 7.5 ns). After
considering the clock jitter, the minimum clock period (Tc1(min)) observed at the pin may be less
than 7.5 ns. The PCI-X class 1 clock jitter specification for mode 1 requires the Tcyc-min to be 7.5
ns with jitter consideration. The same applies for the PCI-X clock generated @ 66 MHz.
No negative impact is expected, when compliant with the routing guidelines.
There is no workaround to adjust the minimum clock period (Tc1(min)) of the PCI-X clocks.
However, the routing guidelines for the PCI-X clock signal take into consideration the effect of the
jitter on the minimum clock period (Tc1(min)). Conforming to the routing guidelines in the 80331
design guide will offset the effect of the marginally reduced minimum clock period (Tc1(min))
towards the setup and hold times. Therefore, for system boards that are compliant with the routing
guidelines, the risk of violating the setup and hold time requirements and any resulting functional
impact, is low. Please refer to the 80331 I/O processor design guide (273823) for further
information on the PCI-X clock routing guidelines.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
61.
Problem:
Implication:
Workaround:
Status:
I2C Control Register reset bit does not function
The I2C Control Register (ICR0 and ICR1) bit 14 is supposed to be used for resetting the I2C unit,
but writing a '1' to this bit does not reset the I2C unit. Writing a '1' to bit 14 has no effect.
The I2C unit cannot be reset by using ICRx.14.
Depends on what needs to be accomplished. Asserting P_RST# or setting BCR.6 will reset the I2C
unit but will also reset the entire chip or the secondary bus/ATU. For an I2C bus lock condition, it
may be cleared by software doing a toggle of the GPOD[11:10] to toggle SCL[1:0] (see non-core
erratum 35). If SDA[1:0] need to be toggled, then an external device or unused GPIO will need to
be used to control this sequence.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
62.
Problem:
Implication:
Workaround:
Status:
Internal Clock Misalignment Can Cause Processor Hang
After a reset, the 80331 can hang during initial accesses to SDRAM, due to a possible clock
misalignment, aggravated by a race condition in the clock divider clear circuit.
A failure will manifest itself as a hang of the I/O processor after reset, during initial accesses to
SDRAM. Subsequent warm or cold resets may clear the condition and allow the 80331 to continue
operation.
In most cases, doing a cold or warm reset will clear this condition. Increasing the 1.5v power
supply will reduce the probability of a processor hang. Intel is screening parts to eliminate the
probability of occurrence (refer to Specification Change #22 “Internal Clock Misalignment” on
page 50).
Fixed. This issue was fixed in the D-1 stepping of the product (this is also related to Specification
Change #22 “Internal Clock Misalignment” on page 50).
63.
Problem:
Spurious DMA0 End-Of-Transfer Interrupt
When the interrupt controller goes from having no interrupts asserted to one or more asserted, there
is a 1-clock cycle window in which the IINTVEC (IRQ Interrupt Vector register; FFFF_E7C8h or
CP6, register 14) or FINTVEC (FIQ Interrupt Vector register; FFFF_E7CCh or CP6, register 15)
may report the value of the INTBASE register (Interrupt Base register; FFFF_E7C0h or CP6,
register 12), which is the vector address for interrupt 0, DMA0 End-of-Transfer.
This condition can occur even if the DMA0 EOT interrupt is masked, INTCTL0.0 = 0.
Specification Update
41