QG80331M500SL9BE Datasheet, PDF (33/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
45.
Problem:
Corrupted byte count and data when crossing 1 MByte boundary in PCI-X to
PCI mode
Scenario - Memory Read Block PCI-X to PCI mode beginning at address 9, 10 or 11 bytes from the
1 MB boundary, with a byte count that crosses the boundary.
In this failing scenario, the check for two DWords away from the boundary relies on the aligned
DWord address of the third DWord. Since the starting address is in the middle of the third DWord,
the case is missed. The result is the PCI read satisfies the byte count by reading across the 1 MB
boundary.
The first split completion on the PCI-X bus is correct data, modified byte count and BCM set. The
second split completion on the PCI-X bus has a corrupted byte count, therefore, the correct data is
sent and additional garbage data is then sent until the corrupt byte count is satisfied.
The corrupted byte count is a result of crossing the 1 MB boundary. The original byte count minus
the byte count captured is less than zero.
Implication:
Workaround:
The failing case is very similar to the previous memory read block case, but the impact to the
requester is different.
Corrupted byte count and additional garbage data is sent to the requester to satisfy the corrupted
byte count. In some cases, other transactions (on the bridge) following the bad split completion can
be corrupted. When the bridge completes sending the corrupted byte count, it frees the buffer space
used by that data. That buffer may contain data for other transactions and that data is lost.
Do not allow PCI-X to PCI memory reads with DWORD unaligned starting address to cross the
1 MByte boundary.
Status:
The starting address must have bits [1:0] equal to 01, 10 or 11 for this erratum to occur. When the
starting address[1:0] = 00, this erratum does not occur.
Fixed. Fixed in D-0 stepping. See the Table , “Summary Table of Changes” on page 9.
46.
Problem:
Implication:
Workaround:
Status:
PCI-X to PCI Memory Read with 4 K byte count and unaligned starting
address
The initiator on the PCI-X side issues a Memory Read Block with 4 K request byte count
(BC=000h), which the bridge terminates with Split Response. The address in this case is not
DWORD aligned (A[1:0] does not = 00b). On the PCI side, the bridge executes the transaction as
Memory Read Multiple, but disconnects after only a single dataphase and does not re-issue the
transaction. No split completion is returned to the PCI-X bus and the transaction permanently
consumes transaction resources.
This can permanently consume transaction resources, and therefore could result in a system hang.
Use addresses that are DWORD aligned or any byte count other than 4 K.
Fixed. Fixed in D-0 stepping. See the Table , “Summary Table of Changes” on page 9
Specification Update
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