QG80331M500SL9BE Datasheet, PDF (30/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
38.
Problem:
Implication:
Workaround:
Status:
32-bit region write corrupts ECC immediately after 64-bit Read-Modify-Write
ECC can be corrupted when the following scenario occurs:
• All of memory is initialized to 0s
• A 32-bit region is enabled.
• Agent A fills the 64-bit memory region with pattern A.
• Agent A does a DDR write to same 64-bit memory region, causing an Read-Modify-Write
(RMW) at the end of the transfer where pattern A is returned as part of the RMW process.
• Immediately thereafter, Agent B does a DDR write to an open region of 32-bit memory. On
DQ[63:32] data is driven to pattern A. The wrong ECC is generated (where the ECC is that of
DQ[63:0] where pattern A is present at the upper half of the bus).
The wrong ECC is generated (where the ECC is that of DQ[63:0] where pattern A is present at the
upper half of the bus).
Turn ECC off or don’t use the 32-bit memory region.
Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.
39.
Problem:
Implication:
Workaround:
Status:
Reset straps incorrectly sampled on the secondary reset
All reset straps are sampled on the rising edge of P_RST#, except the following: MEMTYPE,
P_BOOT16# and CORE_RST#.
When external circuitry is used to dynamically control the reset straps, the timing may cause
incorrect values to be latched.
By default all reset straps have internal pull-ups. When non-default state is required, then an
external 1.5K pull-down resistor should be used. This implementation has no timing requirements.
Otherwise, when external circuitry is used to dynamically control, then make sure the proper level
is provided at the rising edge of S_RST#.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
30
Specification Update