QG80331M500SL9BE Datasheet, PDF (46/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Core Errata
7.
Problem:
Workaround:
Status:
Updating the JTAG parallel registers requires an extra TCK rising edge
The IEEE 1149.1 spec states that the effects of updating all parallel JTAG registers should be seen
on the falling edge of TCK in the Update-DR state. The Intel XScale^® core parallel JTAG registers,
incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like
hold-reset, JTAG break, and vector traps require either an extra TCK cycle by going to
Run-Test-Idle or by cycling through the state machine again in order to trigger the expected
hardware behavior.
When the JTAG interface is polled continuously, this erratum has no effect. When not, an extra
TCK cycle can be caused by going to Run-Test-Idle after writing a parallel JTAG register.
No Fix. See the Table , “Summary Table of Changes” on page 9.
8.
Problem:
Workaround:
Status:
Non-branch instruction in vector table may execute twice after a thumb
mode exception
When an exception occurs in thumb mode and a non-branch instruction is executed at the
corresponding exception vector, that instruction may execute twice. Typically instructions located
at exception vectors must be branch instructions which go to the appropriate handler, but the ARM
architecture allows the FIQ handler to be placed directly at the FIQ vector
(0x0000001c/0xffff001c) without requiring a branch. Because of this bug, the first instruction of
such an FIQ handler may be executed twice when it is not a branch instruction.
When a ‘NOP’ is placed at the beginning of the FIQ handler, the ‘NOP’ executes twice and no
incorrect behavior results. When a branch instruction is placed at the beginning of the handler, it
does not executed twice.
No Fix. See the Table , “Summary Table of Changes” on page 9.
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Specification Update