QG80331M500SL9BE Datasheet, PDF (12/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Summary Table of Changes
Non-Core Errata (Sheet 3 of 3)
Steppings
No.
Page Status
A-1 B-0 C-0 C-1 D-0 D-1
Errata
53
X
X
X
X
XX
38
No Fix
PCI-to-PCI read flow-through with destination TRDY# stalls
can cause data corruption
54
X
X
X
X
38 Fixed S_PCIXCAP PCI mode threshold is too high
55
X
X
X
X
XX
39 No Fix No support for burst I/O and configuration read/writes
56
X
X
X
X
XX
39
No Fix
Read flow through hangs due to disconnect without data at
a buffer boundary.
57
X
X
X
X
XX
39 No Fix P_SERR# not asserted for parity error on AD[63:32]
58
X
X
X
X
XX
39
No Fix
Bus Interface Unit (BIU) claims DAC addresses in the
range of the Memory Mapped Registers (MMR
59
X
X
X
X
XX
40
No Fix
PCIX-to-PCI Memory Read issued as 32-bit, then retried as
64-bit
Tc1(min) of the PCI-X clock observed to be marginally less
60
X
X
X
X
XX
41 No Fix than the requirement specified for the PCI-X (Mode 1,
class1) clock jitter.
61
X
X
X
X
XX
41 No Fix I2C Control Register reset bit does not function
62
X
41 Fixed Internal Clock Misalignment Can Cause Processor Hang.
63
X
X
X
X
XX
41 No Fix Spurious DMA0 End-Of-Transfer Interrupt
12
Specification Update