QG80331M500SL9BE Datasheet, PDF (23/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
18.
Problem:
Implication:
Workaround:
Status:
Watchdog time-outs by the PCI-X bridge may cause data corruption
A watchdog time-out by the PCI-X bridge may cause data loss or corruption in an unrelated
transaction.
Watchdog time-outs can cause data corruption.
Do not enable the watchdog time-out counter (default setting). The Watchdog Timer has been
de-featured from the 80331. See Specification Change #4.
No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.
19.
Problem:
Implication:
Workaround:
Status:
Discard timer expiration on delayed read can cause data corruption or
deadlock when data is still being received on target bus
The discard timer in the PCI-X bridge starts counting when read data is first received. When data
comes in very slowly (for example, when the target bus speed is much slower than the requesting
bus) the discard timer on the requesting bus may elapse before the read data is complete, and cause
state machine errors.
When a delayed read in PCI-to-PCI or PCI-to-PCIX mode receives immediate data on the
destination bus, and the time required to receive that data exceeds the value of the discard timer,
data corruption or deadlock may occur.
Set discard time-out value to 2^15 (default setting) or reduce prefetch settings when bus speeds are
very different.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
20.
Problem:
Implication:
Workaround:
Status:
Configuration cycle attribute parity error signaled incorrectly by PCI-X
bridge
A configuration cycle with an attribute parity error gets a retry response by the PCI-X bridge,
instead of a target abort.
When the SERR# Enable bit (PCR.8) is not set, transient parity errors may go undetected.
Set PCR.8 to enable primary bus SERR# assertions for parity error detection.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
21.
Problem:
Implication:
Workaround:
Status:
Transactions are buffered during Secondary Reset
When the secondary bus is reset by software (i.e., setting the secondary bus reset bit - BCR.6), the
buffer control needs to retry all transactions (except type 0 configuration cycles). The problem is
that the buffer controller is not looking at the secondary reset signal, so when the secondary bus
reset bit is set (S_RST# asserted) the buffers enqueue a transaction that was retried. Instead, it
needs to remain idle until reset is complete, and not enqueue the retried transactions.
May cause data corruption.
After de-asserting S_RST# by clearing (i.e., writing a '0') the Secondary Bus Reset bit (BCR.6),
wait 155 µs before sending a new transaction to the bridge.
Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.
Specification Update
23