QG80331M500SL9BE Datasheet, PDF (10/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Summary Table of Changes
Non-Core Errata (Sheet 1 of 3)
Steppings
No.
Page Status
A-1 B-0 C-0 C-1 D-0 D-1
Errata
1
X
X
X
X
X
X
19
No Fix
CAS latency of three not supported for DDR-II On-Die
Termination (ODT)
2
X
19
Fixed
Upper PCI signals on Secondary PCI bus are not driven
low during reset
3
X
19
Fixed
Memory Controller Unit does not properly support 32-bit
memory configurations
4
X X X X X X 19 No Fix Legacy Power Fail Mechanism does not work
5
X
20 Fixed Boundary Scan data gets inverted
6
X
20
Fixed
BIU interrupt does not occur on Internal Bus Write Master
Abort
7
X
20
Fixed
CRC value calculated by DMA unit is not compliant with
iSCSI
8
X
20
Fixed
ATU Outbound Direct Window overlaps with PBI exception
vectors
9
X
X
X
X
X
X
20
No Fix
S_REQ64# Initialization Pattern Timing Violation in PCI-33
Mode
10
X
21 Fixed PCI-66 Mode violates PCI AC Timings
11
X
21
Fixed
Reserved bits in the Modem Status Register incorrectly
generate interrupts
12
X
21 Fixed P_REQ# not de-asserted during idle
13
X
21 Fixed Chassis/Slot PCI Extended Capability is not valid
14
X
22 Fixed SDCR0.2 implemented as ‘Reserved’
15
X
22 Fixed 32-bit region missing proper address decode
16
X
22
Fixed
S_GNT[3:2]# outputs are not pulled high when Bridge is
disabled.
Split Transaction Commitment limit register mechanism, in
17
X
X
X
X
XX
22
No Fix
the PCI-X bridge, does not operate as implied by the PCI-X
Addendum to the PCI Local Bus Specification,
Revision 1.0a
18
X
X
X
X
XX
23
No Fix
Watchdog time-outs by the PCI-X bridge may cause data
corruption
19
X
Discard timer expiration on delayed read can cause data
23 Fixed corruption or deadlock when data is still being received on
target bus
20
X
23
Fixed
Configuration cycle attribute parity error signaled
incorrectly by PCI-X bridge
21
X
X
22
X
23
X
24
X
X
23 Fixed Transactions are buffered during Secondary Reset
24
Fixed
Primary bus pin mode behavior incorrect during reset in the
80331 no bridge mode
24
Fixed
P_REQ# pin mode behavior when in the 80331 no bridge
mode
Master abort after data transfer within a single ADB on
24 Fixed PCI-X to PCI-X read block transactions may cause data
corruption or deadlock
10
Specification Update