QG80331M500SL9BE Datasheet, PDF (21/67 Pages) Intel Corporation – Intel 80331 I/O Processor Specification Update

Intel^® 80331 I/O Processor
Non-Core Errata
10.
Problem:
Implication:
Workaround:
Status:
PCI-66 Mode violates PCI AC Timings
The PCI Local Bus Specification, Revision 2.3 states a setup time of 3 ns for PCI-66 mode. The
80331 A-1 step has estimated the setup time to be in the range of 3.5 ns to 4 ns, which violates the
PCI Local Bus Specification, Revision 2.3.
Some PCI 66 MHz targets may not function correctly with A-1 stepping.
Use PCI-33 or PCI-X modes for initial development on A-1 stepping.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
11.
Problem:
Implication:
Workaround:
Status:
Reserved bits in the Modem Status Register incorrectly generate interrupts
Bits[3:1] in the UART Modem Status Register are reserved bits. These reserved bits are incorrectly
tied to the asserted state therefore generate false interrupts when the Modem Interrupt Enable bit
(UxIER.3) is set. However, the reserved bits only generate the false interrupt once. This happens
the cycle after the UART unit is enabled (UxIER.6) and the Modem Status Interrupts are enabled
(UxIER.3). Once the Modem Interrupt Register is read no more false interrupts occur.
A false interrupt can occur.
Software needs to read the Modem Status Register to determine proper interrupt sources.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
12.
Problem:
Implication:
Workaround:
Status:
P_REQ# not de-asserted during idle
The P_REQ# signal stays asserted during bus idle instead of de-asserting as required by PCI Local
Bus Specification, Revision 2.3. For example, when a PCI target asserts STOP#, the P_REQ#
signal de-asserts one clock later than it should. The P_REQ# should have been de-asserted during
the idle cycle.
May cause conflict with other PCI agents.
Use a system arbiter that does not care when this condition occurs.
Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.
13.
Problem:
Implication:
Workaround:
Status:
Chassis/Slot PCI Extended Capability is not valid
The Chassis/Slot PCI extended capability cannot be configured, and therefore the capability is not
valid and needs to be removed from the capability chain. The Chassis/Slot capability registers at
D4h - D7h needs to be listed as reserved.
Invalid capability information provided to the host.
Do not use Chassis/Slot PCI Extended Capability.
Fixed. Fixed in B-0 stepping. The fix is to change the capability pointer at 34h to point to the next
capability pointer (Power Management) at DCh, instead of D4h. D4h is to return zero when read.
See the Table , “Summary Table of Changes” on page 9.
Specification Update
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