HYB25D256400BT Datasheet, PDF (9/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456
bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a
single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-
tration of an Active command, which is then followed by a Read or Write command. The address bits regis-
tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
V_DD and V_DDQ are driven from a single power converter output AND
V_TT meets the specification AND
V_REF tracks V_DDQ/2
or
The following relationship must be followed:
V_DDQ is driven after or with V_DD such that V_DDQ < V_DD + 0.3 V
V_TT is driven after or with V_DDQ such that V_TT < V_DDQ + 0.3V
V_REF is driven after or with V_DDQ such that V_REF < V_DDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200ms delay prior to applying an executable command.
Once the 200ms delay has been satisfied, a Deselect or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operat-
ing parameters. 200 clock cycles are required between the DLL reset and any executable command. During
the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock
cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters
without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal
operation.
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2003-01-09, V1.1