HYB25D256400BT Datasheet, PDF (62/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles (tCK=133Mhz) (0 °C £ T_A £ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V,
Symbol
Parameter
sort
t_MRD
t_WPRE
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
Mode register set command cycle time
Write preamble
Active to Precharge command
Active to Active/Auto-refresh command period
DDR266A
DDR266
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
DDR266A
DDR266
Precharge command period
DDR266A
DDR266
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tCK = 133MHz
Min
Max
2
0.25
6
16000
9
8
10
3
2
3
2
2
2
5
1
10
200
Units
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
Notes
1-54
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input ref-
erence level for signals other than CK/CK, is V_REF.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note
3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Page 62 of 77
2003-01-09, V1.1