HYB25D256400BT Datasheet, PDF (6/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Block Diagram (64Mb x 4)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
13
A0-A12,
BA0, BA1
15
2
2
11 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 1024 x 8)
Sense Amplifiers
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
COL0
1
8
8
8
Data
4
4
4
DQS
Generator
COL0 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
2
1
Drivers _{8 4}
4
clk clk
4
4
out in _Data
1
DQS
1
4
CK,
COL0
CK
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Page 6 of 77
2003-01-09, V1.1