HYB25D256400BT Datasheet, PDF (63/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Timing Diagrams
Data Input (Write) (Timing Burst Length = 4)
DQS
DQ
DM
t_DQSL
t_DQSH
t_DH
t_DS
DI n
t_DH
t_DS
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Data Output (Read) (Timing Burst Length = 4)
DQS
DQ
t_{DQSQ max}
t_QH
t_QH (Data output hold time from DQS)
t_DQSQ and t_QH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.
t._DQSQ and t_QH both apply to each of the four relevant edges of DQS.
t_{DQSQ max.} is used to determine the worst case setup time for controller data capture.
t_QH is used to determine the worst case hold time for controller data capture.
Page 63 of 77
2003-01-09, V1.1