HYB25D256400BT Datasheet, PDF (13/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set com-
mand with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A
Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Required CAS Latencies
CK
CK
Command
DQS
DQ
Read
NOP
CL=2
NOP
CAS Latency = 2, BL = 4
NOP
NOP
NOP
CK
CK
Command
DQS
DQ
Read
NOP
CL=2.5
NOP
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
CAS Latency = 2.5, BL = 4
NOP
NOP
NOP
Don’t Care
Page 13 of 77
2003-01-09, V1.1